1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and particularly relates to a manufacturing method of a capacitor electrode with an HSG-processed surface.
2. Description of the Related Art
As semiconductor devices recently become more highly integrated, reducing a cell area is desired. In the case of DRAM in which one bit comprises one transistor and one capacitor, however, if a cell area diminishes, a capacitor electrode area diminishes, data storage time lowers, and it becomes difficult to secure the minimum capacity required for preventing memory loss caused by an alpha ray, etc. To reduce a cell area and at the same time to increase a capacitor electrode area, attempts to create a three-dimensional structure including a cylinder structure shown in FIG. 1(a) and a fin structure shown in FIG. 1(b) were made. A method of coating an amorphous silicon surface by tantalumoxide (Ta2O5) with a high dielectric constant, as shown in FIG. 1(c), or by bariumtitanic acid strontium (Ba(X)Sr(1-x)TiO) with a high dielectric constant, as shown in FIG. 1(d), have been considered, but this method has not been made practicable yet.
Accordingly, an HSG process (hemispherical grained process) (shown in FIG. 1(e)) which increases a surface area by roughening Si on a capacitor electrode surface attracts attention. The HSG process is a method of causing the electrode surface to migrate unevenly by removing a spontaneous oxidation film from the amorphous silicon surface by preprocessing, removing hydrogen from dangling bonds by heating a semiconductor wafer to a processing temperature, forming a selectively active amorphous silicon/polysilicon mixed-phase layer only on the active surface of the amorphous polysilicon, and crystallizing the surface.
If this HSG process is used, however, a problem occurs in that a phosphorus concentration in HSG grain drops occurs, because phosphorus (P) which is doped is more difficult to move than Si when the foundation amorphous silicon migrates. If a C-V measurement is taken at this state, capacitance rating drops on the volume side (depleted), and a Cmin/Cmax ratio worsens to approximately 0.85xcx9c0.40 times the ratio before the HSG formation. With this result, the effects of a surface area increase are lessened.
To solve this problem, conventionally after the HSG formation, it was necessary to supplement P which was deficient by removing a semiconductor wafer from a device and doping PH3 using a separate apparatus. Additionally, as a subsequent process, there was a process of forming a capacity film using SiN. This process, however, also required nitriding treatment in another apparatus and removing a semiconductor wafer from the HSG-forming apparatus.
It is necessary to rinse the semiconductor wafer every time it contacts the atmosphere, hence there were problems that not only the number of processes increased but also a surface area decreased because HSG grain was etched by re-rinsing.
Furthermore, a conventional nitriding temperature is approximately 850xc2x0 C. (1562xc2x0 F.). There is a problem of impurity rediffusion as semiconductor devices become more highly integrated and lowering of a nitriding temperature is necessary.
Consequently, an object of the present invention is to increase capacitance effectively by continuously PH3-annealing a semiconductor wafer without removing it from the apparatus, and further, to provide a method of manufacturing a semiconductor device which excels in stability and reproducibility by performing nitriding at a low temperature.
Additionally, another object of the present invention is to provide a method of manufacturing a semiconductor device which improves productivity by continuously performing PH3-annealing and nitriding without increasing the number of processes.
To solve the above-mentioned problems, the present invention includes, but is not limited to, the following embodiments:
A method of forming a capacitor electrode comprising polysilicon having a rough surface on a semiconductor substrate, comprises (a) a preprocess of removing a spontaneous oxidation film adhering to an amorphous silicon surface, (b) a process of heating the amorphous silicon to a designated temperature, a process of spraying SiH4 at a designated temperature on the amorphous silicon to form an amorphous/polysilicon mixed-phase active layer on the surface, (c) a process of annealing at a designated temperature to form a HSG so as to roughen the amorphous silicon surface, (d) a process of PH3-annealing the HSG-forming polysilicon, wherein PH3 is introduced at a designated concentration at the start of heating to a designated temperature, and (e) a process of nitriding the amorphous silicon surface at a designated temperature by continuously introducing NH3 gas instead of PH3.
Specifically, in an embodiment, the preprocessing may comprise processes of immersion in diluted HF, rinsing with pure water, and drying.
Preferably, a temperature to which the amorphous silicon is heated is 500xc2x0 C.xcx9c600xc2x0 C. (932xc2x0 F.xcx9c1112xc2x0 F.).
Further, preferably, a SiH4 concentration is 30%xcx9c50% in an embodiment. Specifically, in an embodiment, the annealing temperature is 500xc2x0 C.xcx9c600xc2x0 C. (932xc2x0 F.xcx9c1112xc2x0 F.).
Additionally, in the process of PH3-annealing the amorphous silicon, PH3 may be diluted to 0.5%xcx9c5.0%, for example, by inert gases such as nitrogen, argon, and helium, or hydrogen.
Additionally, in another embodiment, during the nitriding process, a mixed gas of NH3 and hydrazine or monomethylehydrazine may be used.
Preferably, the designated temperature for the PH3 annealing and nitriding is 560xc2x0 C.xcx9c750xc2x0 C. (1040xc2x0 F.xcx9c1382xc2x0 F.).
According to an embodiment of the present invention, a capacitor electrode with a larger surface area can be achieved with fewer processes than could be achieved using the conventional method.
Additionally, according to an embodiment of the present invention, a stable capacitor electrode with a controlled progress of migration can be obtained.
For purposes of summarizing the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.
Further aspects, features and advantages of the present invention will become apparent from the detailed description of the preferred embodiments which follow.